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<div class="header">
  <div class="headertitle"><div class="title">RCC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Reset and Clock Control.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Reset and Clock Control. </p>
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<p>RCC AHB1 peripheral clock register, Address offset: 0xD8 </p>

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<p>RCC AHB1 peripheral sleep clock register, Address offset: 0x100 </p>

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<p>RCC AHB1 peripheral reset register, Address offset: 0x80 </p>

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<p>RCC AHB2 peripheral clock register, Address offset: 0xDC </p>

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<p>RCC AHB2 peripheral sleep clock register, Address offset: 0x104 </p>

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<p>RCC AHB2 peripheral reset register, Address offset: 0x84 </p>

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<p>RCC AHB3 peripheral clock register, Address offset: 0xD4 </p>

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<p>RCC AHB3 peripheral sleep clock register, Address offset: 0xFC </p>

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<p>RCC AHB3 peripheral reset register, Address offset: 0x7C </p>

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<p>RCC AHB4 peripheral clock register, Address offset: 0xE0 </p>

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<p>RCC AHB4 peripheral sleep clock register, Address offset: 0x108 </p>

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<p>RCC AHB4 peripheral reset register, Address offset: 0x88 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a60744135b166d9236404b1b252935fe6">&#9670;&#160;</a></span>APB1HENR</h2>

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<p>RCC APB1 peripheral clock High Word register, Address offset: 0xEC </p>

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<p>RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 </p>

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<p>RCC APB1 peripheral reset High Word register, Address offset: 0x94 </p>

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<p>RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 </p>

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<p>RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 </p>

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<p>RCC APB1 peripheral reset Low Word register, Address offset: 0x90 </p>

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<p>RCC APB2 peripheral clock register, Address offset: 0xF0 </p>

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<p>RCC APB2 peripheral sleep clock register, Address offset: 0x118 </p>

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<p>RCC APB2 peripheral reset register, Address offset: 0x98 </p>

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<p>RCC APB3 peripheral clock register, Address offset: 0xE4 </p>

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<p>RCC APB3 peripheral sleep clock register, Address offset: 0x10C </p>

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<p>RCC APB3 peripheral reset register, Address offset: 0x8C </p>

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<p>RCC APB4 peripheral clock register, Address offset: 0xF4 </p>

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<p>RCC APB4 peripheral sleep clock register, Address offset: 0x11C </p>

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<p>RCC APB4 peripheral reset register, Address offset: 0x9C </p>

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<p>RCC Vswitch Backup Domain Control Register, Address offset: 0x70 </p>

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<p>RCC clock configuration register, Address offset: 0x10 </p>

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<p>RCC Clock Source Interrupt Clear Register Address offset: 0x68 </p>

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<p>RCC Clock Source Interrupt Enable Register Address offset: 0x60 </p>

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<p>RCC Clock Source Interrupt Flag Register Address offset: 0x64 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#abcb9ff48b9afb990283fefad0554b5b3">&#9670;&#160;</a></span>CR</h2>

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<p>RCC clock control register, Address offset: 0x00 </p>

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<p>Clock Recovery RC Register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa2d7bfc4c20fea2c980bda5114e31384">&#9670;&#160;</a></span>CSICFGR</h2>

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<p>CSI Clock Calibration Register, Address offset: 0x0C </p>

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<p>RCC clock control &amp; status register, Address offset: 0x74 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7edcbbd70a162b0896b1ee0f465b13b0">&#9670;&#160;</a></span>D1CCIPR</h2>

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<p>RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C </p>

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<p>RCC Domain 1 configuration register, Address offset: 0x18 </p>

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<p>RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9168a7090cfa4125c517c5aaaa3baae1">&#9670;&#160;</a></span>D2CCIP2R</h2>

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<p>RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 </p>

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<p>RCC Domain 2 configuration register, Address offset: 0x1C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ada0be86dd42582ae99b43868fc13c08c">&#9670;&#160;</a></span>D3AMR</h2>

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<p>RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0456a2f98ab35da5c66d2c25ed6b5848">&#9670;&#160;</a></span>D3CCIPR</h2>

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<p>RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 </p>

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<p>RCC Domain 3 configuration register, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5c3f5140ae596eaa834f4f3a85765f95">&#9670;&#160;</a></span>GCR</h2>

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<p>RCC RCC Global Control Register, Address offset: 0xA0 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a17b0cadfbcca7ed3b6aa4ef43c6c12f9">&#9670;&#160;</a></span>HSICFGR</h2>

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<p>HSI Clock Calibration Register, Address offset: 0x04 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a57bcbce85db68d77ed5cbf18a10f9d3f">&#9670;&#160;</a></span>PLL1DIVR</h2>

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<p>RCC PLL1 Dividers Configuration Register, Address offset: 0x30 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2134cb67af4b948e7d6d6c656e8837d2">&#9670;&#160;</a></span>PLL1FRACR</h2>

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<p>RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab258f4bfa80f5c8f6cc5440df30c0909">&#9670;&#160;</a></span>PLL2DIVR</h2>

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<p>RCC PLL2 Dividers Configuration Register, Address offset: 0x38 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad8bccd45fde1d630c5bb4f035e6ea0fb">&#9670;&#160;</a></span>PLL2FRACR</h2>

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<p>RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a59d4bd0595fcfd4ca87cc2dd17e7eb2a">&#9670;&#160;</a></span>PLL3DIVR</h2>

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<p>RCC PLL3 Dividers Configuration Register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afd88563b698968b152eed83be41f0334">&#9670;&#160;</a></span>PLL3FRACR</h2>

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<p>RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 </p>

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<p>RCC PLLs Configuration Register, Address offset: 0x2C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a627836f05c0e3a9545605318e6447adf">&#9670;&#160;</a></span>PLLCKSELR</h2>

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<p>RCC PLLs Clock Source Selection Register, Address offset: 0x28 </p>

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<p>Reserved, Address offset: 0x14 </p>

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<p>Reserved, 0xAC-0xCC Address offset: 0xAC </p>

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<p>Reserved, Address offset: 0xF8 </p>

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<p>Reserved, 0x120-0x12C Address offset: 0x120 </p>

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<p>Reserved, Address offset: 0x24 </p>

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<p>Reserved, Address offset: 0x48 </p>

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<p>Reserved, Address offset: 0x5C </p>

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<p>Reserved, Address offset: 0x6C </p>

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<p>Reserved, Address offset: 0x78 </p>

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<p>Reserved, Address offset: 0xA4 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af24273f1ea29293cf757fc13c5c030ea">&#9670;&#160;</a></span>RSR</h2>

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<p>RCC Reset status register, Address offset: 0xD0 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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